This year the RISC-V Summit was able to bring together participants both online and in person and it was great that we could have representation from Codeplay at the conference with our own booth.
It’s been an interesting year for RISC-V with many processor vendors making major announcements, and we have been seeing a real increase in companies looking at building accelerator processors using the RISC-V ISA. The big news for Codeplay at the Summit was announcing a key partnership with Andes to bring our Acoran software platform to AndesCore.
Beyond this, on the first day my colleagues Alastair Murray and Colin Davidson presented the work we have been doing to bring open standards programming to RISC-V processors that use the RISC-V Vector extension. The Vector extension is important because it provides a very strong choice for high -performance, dense compute capabilities for the data-parallel workloads found in Artificial Intelligence applications and algorithms.
Watch the talk through the RISC-V Summit YouTube channel to discover more and feel free to get in touch with us with any questions you have.
At our booth during the conference, we were showing a demonstration of the ResNet-50 neural network classifying an image running on RISC-V using the Spike simulator. This is the result of a collaboration between our Product Engineering and Research teams to show the full use of our Acoran open acceleration platform.
Our Product Engineering team has developed the Acoran software platform to enable the SYCL open standard programming model that runs using the Spike simulator with a simulated RISC-V Vector extension.
SYCL is a standardized interface that enables software developers to write code that can take full advantage of accelerator architectures, such as GPUs, by running certain parts of their code in parallel. This is especially important for AI and machine learning applications that make use of lots of matrix operations, but these are also commonly used in many other algorithms.
By enabling Acoran software developers can write SYCL or OpenCL code and compile it to run on the Spike simulator, with simulated acceleration and vectorization. Beyond this, Acoran also enables a set of libraries that provide heavily optimized methods for commonly used operations such as linear algebra routines.
Our Research team has developed a deep learning application that take full advantage of the Acoran platform, using ResNet-50, the ONNX open-source formats for neural networks and supporting operations from libraries such as SYCL-BLAS. The result demonstrates how our software stack seamlessly enables acceleration of software on RISC-V using the RISC-V Vector extension.
Currently this software platform runs on the Spike simulator but, following our announcement at the Summit with Andes mentioned earlier in this post, we are eager to bring this to real hardware. If you want to try this software out we can provide you with access; all you need to do is get in touch with us.
I think it’s also worth going into a bit more detail on how we have been working with the RISC-V Vector extension for the past 12 months or so. The RISC-V Vector extension is a crucial piece in enabling vectorization, such as matrix operations or pixel-wise operations, so that the code can be accelerated by running individual operations in parallel across the cores of a processor. However, in order to accelerate this code, it needs to be translated into RISC-V RVV extension instructions that can be understood by the RISC-V processor or simulator.
This gets more interesting when we talk about automatic vectorization. In this scenario the compiler understands how to translate the code into vector instructions for the RVV extension, helping to increase the performance substantially. This automatic vectorization is also invisible to the software developer, so they can focus on writing their algorithms without thinking about how this code will be vectorized on the processor itself.
This year the Barcelona Supercomputing Centre announced the contributions they alongside Codeplay and SiFive made to the LLVM project to support code-generation for RISC-V vectors.
The work our team has been doing required close cooperation with the open source community and a key part of the project is extending the open source LLVM compiler project by implementing a code generation framework responsible for lowering vectorized compiler IR to RVV machine code. It also lays the foundations for our work to enable the Acoran software platform for any RISC-V processor using the RVV extension.